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| Sept. 1995 Edition 1.0a DATA SHEET MB1503 LOW-POWER PLL FREQUENCY SYNTHESIZER WITH POWER SAVE FUNCTION (1.1GHz) The Fujitsu MB1503 is a serial input phase-locked loop (PLL) frequency synthesizer with a pulse-swallow function. A stand-by mode is provided to limit power consumption during intermittent operation. The MB1503 is configured of a 1.1GHz dual-modulus prescaler with 128/129 divide ratio, control signal generator, 16-bit shift register, 15-bit latch, programmable reference divider (binary 14-bit programmable reference counter), 1-bit switch counter, phase comparator with phase conversion function, charge pump, crystal oscillator, 19-bit shift register, 18-bit latch, programmable divider (binary 7-bit swallow counter and binary 11-bit programmable counter), analog switches, and an intermittent operation control circuit that selects the operating or stand-by mode depending on the power-save control input state (PS). The MB1503 operates from a single +5 V supply. Fujitsu's advanced technology achieves an Icc of 8mA, typical. The stand-by mode current consumption is just 100A. Features * * * * * - - * - - * * * * : fIN = 1.1GHz (PIN = -10dBm) : High-speed dual-modulus prescaler with 128/129 divide ratio Low supply current : ICC = 8mA typ. at 5V Power-saving stand-by mode : 100A Serial input, 18-bit programmable divider consisting of: Binary 7-bit swallow counter : 0 to 127 Binary 11-bit programmable counter : 16 to 2,047 Serial input 15-bit programmable reference divider consisting of: Binary 15-bit programmable reference counter: 8 to 16,383 1-bit switch counter sets prescaler divide ratio On-chip analog switch for fast lock-up On-chip charge pump Wide operating temperature range: -40 to +85C Plastic 16-pin dual inline package (Suffix : -P) Plastic 16-pin small outline package (Suffix : -PF) High operating frequency Pulse-swallow function PLASTIC PACKAGE (FPT-16P-M06) ABSOLUTE MAXIMUM RATINGS (See NOTE) Ratings Supply Voltage Output Voltage Output Current Storage Temperature Symbol VCC VP VOUT IOUT Tstg Value -0.5 to +7.0 VCC VP 10.0 -0.5 to VCC +0.5 10 -55 to +125 Unit V V V mA C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. PLASTIC PACKAGE (DIP-16P-M04) NOTE: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Copyright (c) 1994 by FUJITSULIMITED 1 MB1503 PIN ASSIGNMENT (TOP VIEW) OSCIN OSCOUT VP VCC DO GND LD fIN 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 PS fR fP BiSW FC LE Data Clock 2 MB1503 BLOCK DIAGRAM 16 PS OSCIN 1 16-bit Shift Register Oscillator PS1 16-bit Shift Register To Lock Detector Phase Comparator PS1 15 fR OSCOUT 2 15-bit Latch 15-bit Latch 14 fP VP 3 Programmable Reference Divider Binary 14-bit Reference Counter Phase Characteristics Changing Circuit PS1 PS1 Charge Pump VCC 4 S W From Phase Comparator 13 BiSW From Charge Pump DO 5 Intermittent Operation Control Circuit 12 FC GND 6 From Phase Comparator Lock Detection Circuit Schmitt Trigger 11 LE LD 7 19-bit Shift Register 19-bit Shift Register 1-bit Control Latch Schmitt Trigger 10 Data 18-bit Latch 7-bit Latch PS1 Programmable Divider Prescaler Output Binary 7-bit Binary 11-bit Programmable Swallow Counter Counter 11-bit Latch Schmitt Trigger 9 Clock SW fIN 8 Prescaler PS1 MC Control Circuit 3 MB1503 PIN DESCRIPTION Pin No. Pin Name 1 OSCIN I/O I Description Programmable reference divider input Oscillator input An external crystal is connected to this pin. Oscillator output An external crystal is connected to this pin. Power supply input for charge pump and analog switch Power supply Charge pump output The phase of the charge pump is reversed depending on the FC input. Ground Phase comparator output The output level is high when LD is locked. The output level is low when LD is unlocked. Prescaler input Connection with an external VCO should be done by AC coupling. Clock input for 19-bit and 16-bit shift registers Data is shifted into the shift register on the rising edge of the clock.The Schmitt trigger is contained. Serial data input using binary code The last bit of the data is a control bit. When the control bit is high, data is transmitted to the 15-bit latch. When it is low, data is transmitted to the 18-bit latch.The Schmitt trigger input is involved. Load enable signal input When LE is high, the data of the shift register are transferred to a latch, depending on the control bit in the serial data. At the same time, an internal analog switch turns on and the output of the internal charge pump is connected to the BiSW pin.The Schmitt trigger input is involved. Phase select input of phase comparator (with internal pull-up resistor) When FC is low, the characteristics of the charge pump and phase comparator are reversed. The FC input signal is also used to control the fOUT pin (test pin) of fR or fP. Analog switch output BiSW is usually in the high-impedance state. When the switch is turned on (LE is high), the state of the internal charge pump is output. Monitor pin of programmable counter output Monitor pin of reference counter output Power save signal input Set PS low while the system is powered (never use pin 16 as it is opened) PS = High : Operation mode PS = Low : Stand-by mode 2 3 4 5 6 7 8 9 OSCOUT VP VCC DO GND LD fIN Clock O - - O - O I I 10 Data I 11 LE I 12 FC I 13 BiSW O 14 15 16 fP fR PS O O I 4 MB1503 FUNCTIONAL DESCRIPTIONS Pulse swallow function The divide ratio can be calculated using the following equation: fVCO = [(M x N) + A] x fOSC / R (A < N) fVCO : Output frequency of external voltage controlled oscillator (VCO) N : Preset divide ratio of binary 11-bit programmable counter (16 to 2,047) A : Preset divide ratio of binary 7-bit swallow counter (0 A 127) fOSC : Output frequency of the reference frequency oscillator R : Preset divide ratio of binary 14-bit programmable reference counter (8 to 16,383) M : Preset divide ratio of modules prescaler (128) Serial data input Serial data is input using the Data, Clock, and LE pins. Serial data controls the 15-bit programmable reference divider and 18-bit programmable divider separately. Binary serial data is input to the Data pin. One bit of data is shifted into the internal shift registers on the rising edge of the clock. When the load enable pin is high or open, stored data is latched depending on the control data as follows: Control data H L (a) Destination of serial data 15-bit latch 18-bit latch Programmable reference divider ratio The programmable reference divider consists of a 15-bit latch and a 14-bit reference counter. The serial 16-bit data format is shown below: Direction of data shift Control bit LSB S 1 S 2 S 3 S 4 S 5 S 6 Divide ratio setting bit for prescaler MSB S 7 S 8 S 9 S 10 S 11 S 12 S 13 S 14 C SW Divide ratio setting bit for programmable reference counter 5 MB1503 * 14-bit programmable reference counter divide ratio Divide ratio R 8 9 * 16383 S 14 0 0 * 1 S 13 0 0 * 1 S 12 0 0 * 1 S 11 0 0 * 1 S 10 0 0 * 1 S 9 0 0 * 1 S 8 0 0 * 1 S 7 0 0 * 1 S 6 0 0 * 1 S 5 0 0 * 1 S 4 1 1 * 1 S 3 0 0 * 1 S 2 0 0 * 1 S 1 0 1 * 1 (Divide ratio = 8 to 16,383) Notes: 1. Divide ratios less than 8 are prohibited 2. SW: This bit selects the divide ratio of the prescaler SW Low: 128 or 129 (SW must be always be low) 3. S1 to S14: These bits select the divide ratio of the programmable reference counter (8 to 16,383) 4. C: Control bit: Set high 5. Input MSB data first (b) Programmable divider divide ratio The programmable divider consists of a 19-bit shift register, 18-bit latch, 7-bit swallow counter, and 11-bit programmable counter. The serial 19-bit data format is shown below: Direction of data shift Control bit LSB S 1 S 2 S 3 S 4 S 5 S 6 S 7 S 8 S 9 S 10 S 11 S 12 S 13 S 14 S 15 MSB S 16 S 17 S 18 C Divide ratio setting bit for swallow counter Divide ratio setting bit for programmable counter 6 MB1503 * 7-bit swallow counter divide ratio Divide ratio A 0 1 * 127 S 7 0 0 * 1 S 6 0 0 * 1 S 5 0 0 * 1 S 4 0 0 * 1 S 3 0 0 * 1 S 2 0 0 * 1 S 1 0 1 * 1 * 11-bit programmable counter divide ratio Divide ratio N 16 17 * 2047 S 18 0 0 * 1 S 17 0 0 * 1 S 16 0 0 * 1 S 15 0 0 * 1 S 14 0 0 * 1 S 13 0 0 * 1 S 12 1 1 * 1 S 11 0 0 * 1 S 10 0 0 * 1 S 9 0 0 * 1 S 8 0 1 * 1 (Divide ratio = 0 to 127) Notes: 1. 2. 3. 4. 5. (Divide ratio = 16 to 2,047) Divide ratios less than 16 are prohibited for the 11-bit programmable counter S1 to S7: These bits select the divide ratio of the swallow counter (0 to 127) S8 to S18: These bits select the divide ratio of the programmable counter (16 to 2,047) C: Control bit: (Set low) Input MSB data first Serial data input timing * t1 ( 1s) : Data setup time t2 ( 1s) : Data hold time t4 ( 1s) : LE setup time to the rising edge of last clock t3 ( 1s) : Clock pulse width t5 ( 1s) : LE pulse width Data S18 = MSB (SW) (1) S17 (S14) S10 (S8) S9 (S7) S1 = LSB (S1) C: Control bit (C: Control bit) Clock LE t1 t2 t3 t5 1 : Bits enclosed in parentheses are used when the divide ratio of the programmable reference divider is selected. Note: One bit of data is shifted into the shift register on the rising edge of the clock. t4 7 MB1503 Intermittent operation Intermittent operation limits power consumption by shutting down or starting the internal circuits according to their necessity. If device operation resumes uncontrolled, the error signal output from the phase comparator may exceed the limit due to an undefined phase relationship between the reference frequency (fR) and the comparison frequency (fP) and frequency lock is lost. To prevent this, an intermittent operation control circuit is provided to decrease the variation in the locking frequency by forcibly correcting the phase of both frequencies to limit the error signal output. This is done by the PS control circuit. If PS is set high, the circuit enters the operating mode. If PS is set low, operation stops and the device enters the stand-by mode. Each mode is explained below: * * Operating mode (PS =High Level) All circuits are operating, and PLL operation is normal. Stand-by mode (PS = Low level) Circuits that do not affect operation are powered down to limit current consumption. The current in the power save state is typically 100A. At this time, the levels of DO and LD are the same as when the PLL is locked. Since DO is placed in the high-impedance state and the input voltage of the voltage controlled oscillator (VCO) is set to the voltage in the operating mode (when locked) by the time constant of the low-pass filter, the frequency output from the VCO (fVCO) is kept at the locking frequency. The operating and stand-by modes alternate repeatedly. This intermittent operation limits the error signal by forcibly correcting the phase of the reference and comparison frequencies to limit power consumption. The device must be set in the stand-by mode (PS = low) when it is powered up. Relationship between the FC input and phase characteristics The FC pin changes the phase characteristics of the phase comparator. The internal charge pump output level (DO) is reversed, depending on the FC pin input level. The relationship between the FC input level and DO is shown below: FC = High or open fR > fP fR < fP fR = fP 1: High impedance When designing a synthesizer, the FC pin setting depends on the VCO characteristics. H L Z (1) FC = Low L H Z (1) 1 : When the VCO characteristics are similar to 1 , set FC high or open. : When the VCO characteristics are similar to 2 , set FC low. VCO output frequency 2 VCO input voltage 8 MB1503 Phase comparator output waveform (FC = High) fR fP LD H DO fR > fP fR = fP Z L fR < fP fR < fP fR < fP Notes: 1. Phase difference detection range: -2 to +2 2. Spike appearance depends on the charge pump characteristics. Also, the spike is output to diminish dead band. 3. When fR > fP or fR < fP, a spike might not appear depending on the charge pump characteristics. 4. LD is low when the phase difference is tw or more. LD is high when the phase difference is tw or less for three or more cycles (when fOSCIN = 12.8MHz, tw = 625 to 1,250ns). Analog switch The LE signal turns the analog switch on or off. When the analog switch is turned on, the charge pump output (DO) is output through the BiSW pin. When it is turned off, the BiSW pin is in the high-impedance state. When LE = high (when the divide ratio of the internal divider is changed): Analog switch = on When LE = low (normal operating mode): Analog switch = off The LPF time constant can be decreased by inserting an analog switch between LPF1 and LPF2. This decreases the lock-up time when the PLL channel is changed. DO CHP LPF-1 LPF-2 VCO BiSW Analog switch (Control signal LE) 9 MB1503 RECOMMENDED OPERATING CONDITIONS Parameter Symbol VCC Supply Voltage VP Input Voltage Operating Temperature VI TA GND -40 Min 4.5 Value Typ 5.0 VCC VP 8.0 - - VCC +85 Max 5.5 Unit V V V C HANDLING PRECAUTIONS * This device should be transported and stored in anti-static containers. * This is a static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are properly grounded. Cover workbenches with grounded conductive mats. * Always turn the power supply off before inserting or removing the device from its socket. * Protect leads with a conductive sheet when handling or transporting PC boards with devices. 10 MB1503 ELECTRICAL CHARACTERISTICS Parameter Symbol Min Value Typ Max Unit Condition With fIN = 1.1GHz, OSCIN = 12MHz, VCC = 5.0V. Inputs are VCC and outputs are open. With fIN = 1.1GHz, OSCIN = 12MHz, VCC = 5.0V. The PS pin is grounded, remaining inputs are at VCC, and outputs are open. AC coupling. The minimum operating frequency is measured with a 100pF capacitor connected. -- -- -- -- -- -- -- -- -- VCC = 5V -- VDO = GND to 8V VCC VP 8V -- -- -- Supply Current ICC - 8.0 12.0 mA Stand-by Current IPS - 100 - A fIN Operating Frequency OSCIN fIN Input Sensitivity OSCIN High-level Input Voltage Low-level Input Voltage High-level Input Current Except fIN and OSCIN Data, Clock, LE FC Input Current High-level Output Voltage Low-level Output Voltage High-impedance Cut off Current Output Current OSCIN Except DO and OSCOUT DO Except DO and OSCOUT fIN 10 - 1100 MHz fOSC Pf IN VOSC VIH VIL IIH IIL IFC IOSC VOH VOL IOFF IOH IOL RON - -10 0.5 VCC x 0.7 - - - - - 4.4 - - -1.0 1.0 - 12 - - - - 1.0 -1.0 -60 50 - - - - - 25 20 6 - - VCC x 0.3 - - - - - 0.4 1.1 - - - MHz dBm Vp-p V V A A A A V V A mA mA Low-level Input Current Analog Switch ON Resistance 11 MB1503 TEST CIRCUIT (FOR MEASURING PRESCALER INPUT SENSITIVITY) 0.1 1000p P*G 50 8 7 6 5 4 VCC = 5V X' tal VP = 6V 3 2 1 VCC = 5V 9 10 11 12 13 14 15 16 Oscilloscope 12 MB1503 APPLICATION EXAMPLE Output LPF VCO From controller PS 16 fR 15 fP 14 BiSW FC 13 12 LE 11 Data 10 9 Clock 47K 47K MB1513 1 OSCIN X' tal C1 2 3 OSCOUT VP 4 VCC 5V 5 DO 6 7 GND LD 8 fIN 1000p 6V C2 0.1 VP, VPX : C1, C2 : Maximum 8V Depends on the crystal parameters 13 MB1503 PACKAGE DIMENSIONS 16-LEAD PLASTIC FLAT PACKAGE (CASE No.: FPT-16P-M06) .400 +.010 (10.15+0.25 ) -.008 -0.20 .089(2.25)MAX (MOUNTING HEIGHT) .002(0.05)MIN (STAND OFF HEIGHT) INDEX "B" .307.016 (7.800.40) .209.012 (5.300.30) .268 +.016 (6.80 +0.40 ) -.008 -0.20 .020.008 (0.500.20) .050(1.27) TYP .018.004 (0.450.10) O.005(0.13) M .006 +.002 (0.15 +0.05 ) -.001 -0.02 "A" Details of "A" part .016(0.40) Details of "B" part .006(0.15) .004(0.10) .350(8.89) REF .008(0.20) .007(0.18) MAX .027(0.68) MAX .008(0.20) .007(0.18) MAX .027(0.68) MAX Dimensions in inches (millimeters) (c)1991 FUJITSU LIMITED F16015S-2C 14 MB1503 16-LEAD PLASTIC DUAL IN-LINE PACKAGE (CASE No.: DIP-16P-M04) .770 +.008 (19.55 +0.20 ) -.012 -0.30 15MAX INDEX-1 .244.010 (6.200.25) .300(7.62) TYP INDEX-2 .039 +.012 -0 (0.99 +0.30 ) -0 .060 +.012 -0 (1.52 +0.30 ) -0 .010.002 (0.250.05) .172(4.36)MAX .118(3.00)MIN .100(2.54) TYP .050(1.27) MAX .018.003 (0.460.08) Dimensions in inches (millimeters) .020(0.51)MIN (c)1991 FUJITSU LIMITED D16033S-2C 15 |
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